1. Field of the Invention
The invention concerns synchronization of synchronous digital bit streams.
2. Description of the Prior Art
It is known to transmit information over a line in the form of a binary bit stream and processing of the information often entails reading the binary bit stream by means of the associated clock signal. This reading is generally effected by means of a D type flip-flop. The information is read on the rising or falling edge of the clock signal driving the flip-flop and passed to the output of the flip-flop. For the reading to be effected correctly the information has to be present for at least a setup time before the active (rising or falling) edge of the clock signal and for at least a hold time after this edge.
When there is more than one bit stream, each bit stream being transmitted by a respective line, the bit streams are made synchronous, in accordance with CCITT Recommendation G. 701, when their significant instants occur at exactly the same rate on average, the bit streams possibly being affected by amplitude jitter lying between specified limits.
It is therefore possible to read synchronous digital bit streams by means of a common clock signal running at the rate at which the significant instants of the bit streams occur, provided that the conditions in respect of setup and hold times are respected. As a general rule these conditions do not raise any problem when the information is at a low bit rate. On the other hand, it becomes necessary to synchronize the bit streams when the hold and setup times and the spread in propagation time in the logic circuits and amplifiers sending the bit streams and in the transmission lines are no longer negligible in comparison with the bit duration, in other words when the bit streams have a high bit rate.
An object of the invention is to synchronize synchronous digital bit streams, in particular to enable them to be read by a common clock signal.